`include "defines.v"
module brunchAddressQueue#(
  parameter Depth = 4
)(
  input clk,
  input rst_n,
  input ctrl_baq_flush_i,
  // In Quene
  input  ifu_baq_valid_i,
  output baq_ifu_ready_o,
  input [`VADDR_W-1:0] ifu_baq_din_i,
  // Out Queue
  output baq_bru_valid_o,
  input  bru_baq_ready_i,
  output [`VADDR_W-1:0] baq_bru_dout_o
); 

  reg [`VADDR_W-1:0] fifo_reg [0:Depth-1];
  reg [$clog2(Depth):0] wr_ptr;
  reg [$clog2(Depth):0] rd_ptr;
  wire full,empty;
  wire wen,ren;

  always@(posedge clk or negedge rst_n)
    if(~rst_n)
      wr_ptr <= 'd0;
    else if(ctrl_baq_flush_i)
      wr_ptr <= 'd0;
    else if(wen && ~full)
      wr_ptr <= wr_ptr + 1'b1;

  always@(posedge clk or negedge rst_n)
    if(~rst_n)
      rd_ptr <= 'd0;
    else if(ctrl_baq_flush_i)
      rd_ptr <= 'd0;
    else if(ren && ~empty)
      rd_ptr <= rd_ptr + 1'b1;

  always@(posedge clk )
    if(wen && ~full)
      fifo_reg[wr_ptr[$clog2(Depth)-1:0]] <= ifu_baq_din_i;
  
  assign baq_bru_dout_o = fifo_reg[rd_ptr[$clog2(Depth)-1:0]];

  assign full      = ( rd_ptr[$clog2(Depth)-1:0] == wr_ptr[$clog2(Depth)-1:0] ) && (rd_ptr[$clog2(Depth)] != wr_ptr[$clog2(Depth)]);
  assign empty     = rd_ptr == wr_ptr;
  assign wen       = ifu_baq_valid_i;
  assign ren       = bru_baq_ready_i;
  assign baq_ifu_ready_o  =  ~full;
  assign baq_bru_valid_o  =  ~empty;

endmodule